Semiconductor integrated circuits are extremely susceptible to gate oxide breakdown caused by electrostatic discharge (ESD). This type of voltage sensitivity has resulted in on-chip electrostatic discharge protection for most semiconductor integrated circuits that use MOS technology. In addition to the electrostatic discharge problem, the susceptibility of semiconductor integrated circuits to electrical overstress (EOS) increases as the integrated circuit is scaled down to sub-micron feature size.
In one of the prior arts, an electrostatic discharge (ESD) protection circuit is disclosed to include protecting transistors configured to float the well and the gate of the protection transistor when no power supply potential (Vcc) is present. The protecting transistors are configured to couple the well and the gate of the protecting transistors to circuit ground (or the power supply potential) when the normal power supply potential (Vcc) is present. However, in this configuration, an ESD event can still cause permanent damage to the protection transistors when they are floating or when they are not connected to the power supply potential (Vcc). In addition, the ESD protection circuit of this prior art requires a large amount of space to implement in the semiconductor integrated circuits.
In another prior art, an integrated circuit having an electrostatic discharge (ESD) protection circuit including a core protection circuit, a sensitive core circuit and peripheral circuitry is disclosed. The core protection of the prior art is configured to disconnect the VCC voltage supply terminal from the VDD voltage supply terminal when the VCC voltage exceeds the nominal VDD supply voltage by a predetermined voltage amount. This ESD protection circuit is cumbersome and does not fully protect the sensitive core circuit from the electrostatic discharge event and the electrical overstress (EOS) because the predetermined voltage amount above the nominal supply voltage (VDD) is fixed. Often, the voltage supply spikes in an electrostatic discharge (ESD) event are different from those in an electrical overstress (EOS) condition and they may occur on the VDD supply voltage.
Thus, there is a need for an electrostatic discharge (ESD) protection circuit that can discharge the excess electrostatic discharge (ESD) voltage to ground at a lower voltage than in the normal operating condition when the electrostatic event occurs so as to fully protect the integrated circuit from the ESD voltage and EOS events. Furthermore, there is a need in the art for an ESD protection that can be fabricated on the same chip with the integrated circuit to be protected.